Job Details:

Job Description: 

About the Team

The Hard IP Development Group (HIPD) within Intel's Central Engineering Organization is responsible for developing leadership IPs that are power-winning products for Server, Client, and Networking SOCs, as well as Intel Foundry Customers. HIPD develops a broad portfolio of Serial and Parallel IO PHYs including PCIe, USB, TypeC, UCIe Die-to-Die, DDR/LPDDR, and Ethernet PHYs.

The Electrical Validation and Debug group within HIPD is a dynamic and versatile team of engineers who directly engage with both IP design teams and SOC customers in IP validation and debug for test chips and products. These engineers embody our SOC customer obsession by validating mixed signal IPs and quickly resolving hurdles through hands-on debug.

This position is exciting and challenging, offering the opportunity to exercise your mixed signal design, architecture, and post-silicon debug expertise across all HIPD IPs, Client, and Server SOC teams.

Position Overview

This role focuses on mixed signal high-speed PHY post-silicon validation and debug, spanning IP enabling, customer sighting resolution, and cross-functional collaboration with SOC teams.

Key Responsibilities

• Generate test plans and test content for mixed signal high-speed PHY post-silicon validation, including characterization of Clocking, Transmitter, and Receiver blocks

• Perform IO protocol debug across one or more of the following: PCIe, UCIe, DDR, or Ethernet, from both PHY recipe and firmware perspectives

• Conduct SOC board design reviews, provide recommendations, and support post-silicon debug activities

• Represent the IP team during SOC Power-Ons for test chips and products, providing hands-on IP enabling support through proper recipes and firmware versions for PCIe, UCIe, and USB PHYs

• Identify clocking and PHY-related silicon issues, investigate, debug, and disposition customer bugs and sightings in a timely manner

• Reproduce customer issues and drive root cause analysis through failure analysis and structured debug methodologies

You Should Demonstrate the Following Professional Traits to Be Successful

• Customer obsession with a strong sense of urgency in resolving technical issues
• Versatility and adaptability when engaging across multiple teams, IPs, and debug scenarios
• Collaborative mindset with the ability to work effectively with both IP design teams and SOC customers

Qualifications:

Minimum Qualifications

• BS with 6+ years, MS with 4+ years, or PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or a related field

• Relevant years of experience (as outlined above) in electrical or bench post-silicon validation with one or more high-speed PHYs such as PCIe, USB, UCIe, DDR, Ethernet, or equivalent interface experience

The experience must also include:

• Experience with lab hardware and software including Oscilloscopes, Logic Analyzers, Protocol Analyzers, and BERTs

• Knowledge of one or more industry-standard IO specifications such as PCIe, USB, or Die-to-Die UCIe

Preferred Qualifications

• Experience with mixed signal IP characterization including PLLs, TX and RX jitter characterization

• Experience leading IP debug efforts as situations arise, in addition to hands-on debug execution

• Signal integrity and power delivery knowledge

• Pre-silicon design or simulation experience in logic, circuits, firmware, MRC, or mixed signal validation

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Folsom

Additional Locations:

US, California, Santa Clara

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

 

 

Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.